Along with the development of light-weight and small-profile electronic products, semiconductor packages serving as core components of the electronic products have accordingly been miniaturized in size. Preferably, the semiconductor packages with a reduced size, fine-pitch interconnections and high-density I/O (input/output) connections, such as a flip-chip package, ball grid array (BGA) package, and chip size package (CSP), etc., have become mainstream package products in the market.
For example, in a conventional flip-chip semiconductor package 10 shown in FIG. 1, a plurality of bumps 101 are formed on an active surface of a semiconductor element 103 such as a semiconductor chip or wafer, and corresponding electrical connection pads are disposed on a carrier 105 such as a substrate or circuit board. The semiconductor element 103 is mounted on the carrier 105 in a face-down manner that the active surface of the semiconductor element 103 faces downwardly and the bumps 101 are bonded to the electrical connection pads on the carrier 105, such that the semiconductor element 103 is electrically connected to the carrier 105 via the bumps 101, and signals from the semiconductor element 103 can be transmitted to the carrier 105.
In order to prevent short circuit caused by melting and bridging of the plurality of bumps 101 during a subsequent high-temperature reflow process, U.S. Pat. No. 6,038,136 has disclosed the use of an underfill material 107 such as resin for filling spaces between the adjacent bumps 101, so as to isolate the bumps 101 from each other and enhance the bonding strength between the bumps 101 and the carrier 105.
However, since the functionality of the semiconductor element has become more complicated, the bumps are accordingly arranged in higher density. As a result, a pitch between adjacent bumps has been reduced from 250 μm to 200 μm, or even to 150 μm. Particularly for the conventional ball-shaped bumps 101 shown in FIG. 1, the spaces between the adjacent bumps 101 would be too small to be completely filled with the underfill material 107 due to the bump shape, and thus causes voids being formed between the adjacent bumps 101. This adversely affects the reliability of the semiconductor package, and even leads to bridging or short circuit of the bumps 101 after the reflow process.
In light of the foregoing drawbacks, U.S. Pat. No. 5,698,465 or 6,555,296 has disclosed the use of pillar bumps to increase spacing between adjacent bumps and maintain a height between the semiconductor element and the carrier, so as to solve the above problem of incomplete filling of the underfill material in the small spaces between adjacent bumps. As shown in FIG. 2, for fabricating a bump structure disclosed in U.S. Pat. No. 5,698,465, an under bump metallurgy (UBM) layer 205 is firstly formed on a bond pad 207 of a semiconductor element such as a chip. Then, a specific pillar bump 201 is formed on the UBM layer 205, and a solder material 203 is applied on the pillar bump 201 by a printing or electroplating technique. Subsequently, the solder material 203 is subjected to a reflow process to electrically connect the pillar bump 201 to a corresponding electrical connection pad on a carrier.
The pillar bump 201 can desirably maintain the height between the semiconductor element and the carrier, however it has a limited effect on increasing the spacing between adjacent pillar bumps. Particularly when the number of I/O connections of the semiconductor element is increased and the pitch between adjacent pillar bumps is reduced to below about 150 μm, the similar drawback is produced that the underfill material fails to penetrate and fill small spaces between the adjacent pillar bumps, thereby causing the problem of voids or short circuit, etc.
Therefore, the problem to be solved here is to provide a bump structure of a semiconductor package, which can avoid the above drawbacks in the prior art.